2778 search results - page 156 / 556 » Reuse Technique in Hardware Design |
157
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ISQED
2008
IEEE
16 years 23 days ago
2008
IEEE
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
161
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—It is generally acknowledged that nanoelectronics will eventually replace traditional silicon CMOS in high-performance integrated circuits. To that end, considerable investments...
173
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DATE
2006
IEEE
16 years 13 days ago
2006
IEEE
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
140
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ATS
2005
IEEE
16 years 10 hour ago
2005
IEEE
In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell...
172
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ITC
1992
IEEE
15 years 10 months ago
1992
IEEE
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...