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DATE
2009
IEEE
83views Hardware» more  DATE 2009»
16 years 1 months ago
Performance-driven dual-rail insertion for chip-level pre-fabricated design
In recent years, pre-fabricated design styles grow up rapidly to amortize the mask cost. However, the interconnection delay of the pre-fabricated design styles slows down the circ...
Fu-Wei Chen, Yi-Yu Liu
ICECCS
2005
IEEE
92views Hardware» more  ICECCS 2005»
15 years 12 months ago
Secure Software Architectures Design by Aspect Orientation
Security design at architecture level is critical to achieve high assurance software systems. However, most security design techniques for software architectures were in ad hoc fa...
Huiqun Yu, Dongmei Liu, Xudong He, Li Yang, Shu Ga...
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 10 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...
ASPDAC
2001
ACM
82views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Towards the logic defect diagnosis for partial-scan designs
Loical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the la...
Shi-Yu Huang
ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
15 years 4 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...