2778 search results - page 152 / 556 » Reuse Technique in Hardware Design |
145
click to vote
DSD
2006
IEEE
16 years 13 days ago
2006
IEEE
Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis...
143
click to vote
ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64TM microprocessor with 90nm CMOS technology. It focuses on the newly adopted t...
174
click to vote
ICCAD
2008
IEEE
16 years 24 days ago
2008
IEEE
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuit...
180
click to vote
DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
— This paper introduces a graph grammar based approach to automated topology synthesis of analog circuits. A grammar is developed to generate circuits through production rules, t...
152
click to vote
ICECCS
2005
IEEE
15 years 12 months ago
2005
IEEE
For Model Driven Development approaches to succeed, there is a need for model validation techniques. This paper presents an approach to testing designs described by UML class diag...