2778 search results - page 137 / 556 » Reuse Technique in Hardware Design |
151
click to vote
TCAD
2010
15 years 1 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
155
click to vote
GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
139
click to vote
ASPDAC
2006
ACM
16 years 9 days ago
2006
ACM
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
188
click to vote
VISSYM
2004
15 years 7 months ago
2004
This paper reports on a new approach for visualizing multi-field MRI or CT datasets in an immersive environment with medical applications. Multi-field datasets combine multiple sc...
180
click to vote
RTAS
2006
IEEE
2006
IEEE
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
16 years 10 days ago
Multiprocessor systems present serious challenges in the design of real-time systems due to the wider variation of execution time of an instruction sequence compared to a uniproce...