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ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
16 years 3 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
DATE
2009
IEEE
148views Hardware» more  DATE 2009»
16 years 1 months ago
A new design-for-test technique for SRAM core-cell stability faults
—Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern...
Alexandre Ney, Luigi Dilillo, Patrick Girard, Serg...
ISCA
2006
IEEE
145views Hardware» more  ISCA 2006»
15 years 6 months ago
Techniques for Multicore Thermal Management: Classification and New Exploration
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
James Donald, Margaret Martonosi
MSE
2005
IEEE
111views Hardware» more  MSE 2005»
15 years 12 months ago
Real World SOC Experience for the Classroom
System-on-Chip design is an important new trend in the design of complex integrated circuits. The integration of a microprocessor, memory and peripherals onto a single die opens n...
Johannes Grad, James E. Stine, David D. Neiman
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
16 years 1 months ago
A real-time application design methodology for MPSoCs
This paper presents a novel technique for the modeling, simulation, and analysis of real-time applications on MultiProcessor Systems-on-Chip (MPSoCs). This technique is based on a...
Giovanni Beltrame, Luca Fossati, Donatella Sciuto