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» Reuse Technique in Hardware Design
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DATE
2008
IEEE
77views Hardware» more  DATE 2008»
16 years 24 days ago
Re-Examining the Use of Network-on-Chip as Test Access Mechanism
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...
Feng Yuan, Lin Huang, Qiang Xu
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 10 months ago
Control generation for embedded systems based on composition of modal processes
In traditional distributed embedded system designs, control information is often replicated across several processes and kept coherent by application-specific mechanisms. Conseque...
Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Bo...
CODES
2001
IEEE
15 years 10 months ago
A practical tool box for system level communication synthesis
This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on ...
Denis Hommais, Frédéric Pétro...
PROCEDIA
2010
66views more  PROCEDIA 2010»
15 years 4 months ago
Parallel signal processing with S-Net
We argue that programming high-end stream-processing applications requires a form of coordination language that enables the designer to represent interactions between stream-proce...
Frank Penczek, Stephan Herhut, Clemens Grelck, Sve...
TIM
2010
188views Education» more  TIM 2010»
15 years 1 months ago
An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems
Abstract--The most popular representative devices of reconfigurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse...
Kyprianos Papadimitriou, Antonis Anyfantis, Aposto...