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» Reuse Technique in Hardware Design
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LCTRTS
2010
Springer
15 years 4 months ago
RNFTL: a reuse-aware NAND flash translation layer for flash memory
In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our bas...
Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao...
KBSE
2007
IEEE
16 years 18 days ago
Automated detection of api refactorings in libraries
Software developers often do not build software from scratch but reuse software libraries. In theory, the APIs of a library should be stable, but in practice they do change and th...
Kunal Taneja, Danny Dig, Tao Xie
SOSP
1997
ACM
15 years 7 months ago
The Flux OSKit: A Substrate for Kernel and Language Research
Implementing new operating systems is tedious, costly, and often impractical except for large projects. The Flux OSKit addresses this problem in a novel way by providing clean, we...
Bryan Ford, Godmar Back, Greg Benson, Jay Lepreau,...
DATE
2006
IEEE
116views Hardware» more  DATE 2006»
16 years 11 days ago
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation
This paper presents a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifier...
Mohammad Yavari, Omid Shoaei, Ángel Rodr&ia...
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 11 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri