2778 search results - page 125 / 556 » Reuse Technique in Hardware Design |
141
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
173
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APCCAS
2006
IEEE
16 years 11 days ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
131
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DATE
2000
IEEE
15 years 10 months ago
2000
IEEE
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper in...
169
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DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
15 years 10 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
154
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DSD
2009
IEEE
15 years 10 months ago
2009
IEEE
This paper addresses the design issue of System-onelevating the design abstraction levels, through a model-driven approach. It considers the standard Marte profile, which is dedic...