2778 search results - page 117 / 556 » Reuse Technique in Hardware Design |
153
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DATE
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
131
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ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
132
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ICCD
2000
IEEE
16 years 3 months ago
2000
IEEE
This paper presents a very general, exact technique for scheduling looping data-flow graphs. In contrast to the conventional technique using loop iteration variables and integer ...
140
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. Th...
162
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FPGA
2007
ACM
16 years 14 days ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...