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ASPDAC
1999
ACM
112views Hardware» more  ASPDAC 1999»
15 years 10 months ago
Relaxed Simulated Tempering for VLSI Floorplan Designs
In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new...
Jason Cong, Tianming Kong, Dongmin Xu, Faming Lian...
ICCAD
1994
IEEE
80views Hardware» more  ICCAD 1994»
15 years 10 months ago
Macromodeling of analog circuits for hierarchical circuit design
{ Hierarchy plays a signi cant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible ...
Jianfeng Shao, Ramesh Harjani
SAMOS
2007
Springer
16 years 12 days ago
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder
Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of...
Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mar...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 10 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
15 years 10 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...