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» Reuse Technique in Hardware Design
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ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
15 years 8 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
16 years 10 days ago
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
Yu Zhou, Danil Sokolov, Alexandre Yakovlev
ACSD
2006
IEEE
109views Hardware» more  ACSD 2006»
15 years 8 months ago
Synthesis of Synchronous Interfaces
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
Purandar Bhaduri, S. Ramesh
EUROMICRO
2002
IEEE
15 years 11 months ago
Developing, Validating and Evolving an Approach to Product Line Benefit and Risk Assessment
1 Product line engineering is usually a very beneficial, but sometimes also a very risky endeavor, as there is no guarantee for economic success. In this paper, we will describe an...
Klaus Schmid, Isabel John
DAC
1996
ACM
15 years 10 months ago
Test Point Insertion: Scan Paths through Combinational Logic
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...