2778 search results - page 111 / 556 » Reuse Technique in Hardware Design |
193
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ICIP
2007
IEEE
16 years 15 days ago
2007
IEEE
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...
156
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ISCA
2000
IEEE
15 years 10 months ago
2000
IEEE
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
142
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DATE
2007
IEEE
16 years 19 days ago
2007
IEEE
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
183
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AHS
2006
IEEE
16 years 11 days ago
2006
IEEE
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...
176
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IWSOC
2005
IEEE
15 years 12 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...