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» Reuse Technique in Hardware Design
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ASPDAC
2000
ACM
109views Hardware» more  ASPDAC 2000»
15 years 10 months ago
A technique for QoS-based system partitioning
Quality of service (QoS) has been an important topic of many research communities. Combined with an advanced and retargetable compiler, variability of applicationsspecific very lar...
Johnson S. Kin, Chunho Lee, William H. Mangione-Sm...
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
16 years 3 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
EH
2002
IEEE
105views Hardware» more  EH 2002»
15 years 11 months ago
Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic
The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5GHz have been reported. However, to make the idea practical, serious power management an...
Channakeshav, Kuan Zhou, Russell P. Kraft, John F....
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
15 years 11 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
CEC
2003
IEEE
15 years 10 months ago
A modified ant colony algorithm for evolutionary design of digital circuits
Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biologi...
Mostafa Abd-El-Barr, Sadiq M. Sait, Bambang A. B. ...