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» Reuse Technique in Hardware Design
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IWSOC
2005
IEEE
141views Hardware» more  IWSOC 2005»
15 years 11 months ago
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
Kenneth A. Townsend, James W. Haslett, Krzysztof I...
DATE
2000
IEEE
117views Hardware» more  DATE 2000»
15 years 10 months ago
Evaluating System Dependability in a Co-Design Framework
The widespread adoption of embedded microprocessor-based systems for safety critical applications mandates the use of co-design tools able to evaluate system dependability at ever...
Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza...
EH
1999
IEEE
170views Hardware» more  EH 1999»
15 years 10 months ago
A Comparison of Dynamic Fitness Schedules for Evolutionary Design of Amplifiers
High-level analog circuit design is a complex problem domain in which evolutionary search has recently produced encouraging results. However, little is known about how to best str...
Jason D. Lohn, Gary L. Haith, Silvano Colombano, D...
ISLPED
2000
ACM
92views Hardware» more  ISLPED 2000»
15 years 9 months ago
Low power sequential circuit design by using priority encoding and clock gating
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
Xunwei Wu, Massoud Pedram
IEEEPACT
2007
IEEE
16 years 15 days ago
Architectural Support for the Stream Execution Model on General-Purpose Processors
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mende...