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DAC
2006
ACM
16 years 7 months ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
16 years 20 days ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
16 years 17 days ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
CCGRID
2005
IEEE
16 years 7 days ago
Cluster security with NVisionCC: process monitoring by leveraging emergent properties
We have observed that supercomputing clusters made up of commodity off-the-shelf computers possess emergent properties that are apparent when these systems are considered as an in...
Gregory A. Koenig, Xin Meng, Adam J. Lee, Michael ...
LSGRID
2004
Springer
15 years 12 months ago
Mega Process Genetic Algorithm Using Grid MP
In this study, a new Genetic Algorithm (GA) using the Tabu · Local Search mechanism is proposed. The GA described in this paper is considered a Mega Process GA, which has an effe...
Yoshiko Hanada, Tomoyuki Hiroyasu, Mitsunori Miki,...