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VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
16 years 7 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
ICDE
2010
IEEE
292views Database» more  ICDE 2010»
16 years 6 months ago
Exploring Power-Performance Tradeoffs in Database Systems
With the total energy consumption of computing systems increasing in a steep rate, much attention has been paid to the design of energy-efficient computing systems and applications...
Zichen Xu, Yi-Cheng Tu, Xiaorui Wang
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
16 years 3 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
214
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IPSN
2010
Springer
16 years 1 months ago
On-line sensing task optimization for shared sensors
Shared sensing infrastructures that allow multiple applications to share deployed sensors are emerging and Internet protocol based access for such sensors has already been prototy...
Arsalan Tavakoli, Aman Kansal, Suman Nath
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
16 years 1 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson