This paper presents a new active queue management scheme, Fuzzy Explicit Marking (FEM), implemented within the differentiated services (Diff-Serv) framework to provide congestion ...
Chrysostomos Chrysostomou, Andreas Pitsillides, Ge...
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper ...
Karthikeyan Sankaralingam, Stephen W. Keckler, Wil...
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Most research on QoS-aware computing considers systems where code is generally partitioned into separately schedulable tasks with associated timing constraints. In sharp contrast ...
Ronghua Zhang, Tarek F. Abdelzaher, John A. Stanko...