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» Requirements and design of a dynamic Grid networking layer
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ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
16 years 27 days ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
16 years 21 days ago
Thermally robust clocking schemes for 3D integrated circuits
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Ta...
HCI
2007
15 years 7 months ago
Online Analysis of Hierarchical Events in Meetings
Automatic online analysis of meetings is very important from three points of view: serving as an important archive of a meeting, understanding human interaction processes, and prov...
Xiang Zhang, Guangyou Xu, Xiaoling Xiao, Linmi Tao
CONEXT
2005
ACM
15 years 8 months ago
Janus: an architecture for flexible access to sensor networks
We present the design and implementation of the Janus1 architecture for providing flexible and lightweight access to sensor network resources from Internet-type networks. Janus p...
Richard Gold
SOCC
2008
IEEE
106views Education» more  SOCC 2008»
16 years 22 days ago
Nanoscale on-chip decoupling capacitors
— A distributed on-chip decoupling capacitor network is proposed in this paper to replace one large capacitor. A system of distributed on-chip decoupling capacitors is shown to p...
Mikhail Popovich, Eby G. Friedman