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» Requirements Processes: An Experience Report
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BMCBI
2010
136views more  BMCBI 2010»
15 years 6 months ago
The IronChip evaluation package: a package of perl modules for robust analysis of custom microarrays
Background: Gene expression studies greatly contribute to our understanding of complex relationships in gene regulatory networks. However, the complexity of array design, producti...
Yevhen Vainshtein, Mayka Sanchez, Alvis Brazma, Ma...
CCS
2006
ACM
15 years 10 months ago
RoleMiner: mining roles using subset enumeration
Role engineering, the task of defining roles and associating permissions to them, is essential to realize the full benefits of the role-based access control paradigm. Essentially,...
Jaideep Vaidya, Vijayalakshmi Atluri, Janice Warne...
ICDCS
2012
IEEE
13 years 9 months ago
Combining Partial Redundancy and Checkpointing for HPC
Today’s largest High Performance Computing (HPC) systems exceed one Petaflops (1015 floating point operations per second) and exascale systems are projected within seven years...
James Elliott, Kishor Kharbas, David Fiala, Frank ...
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
16 years 1 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
CODES
2007
IEEE
16 years 29 days ago
ESL design and HW/SW co-verification of high-end software defined radio platforms
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...
A. C. H. Ng, J. W. Weijers, Miguel Glassee, Thomas...