We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-ofthe-art SAT solvers like Chaff on important problem ...
Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao ...
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
The fault-prone module detection in source code is of importance for assurance of software quality. Most of previous fault-prone detection approaches are based on software metrics...