Sciweavers

10908 search results - page 1906 / 2182
» Requirements Engineering Tasks
Sort
View
CGO
2004
IEEE
15 years 10 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
CGO
2004
IEEE
15 years 10 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
CODES
2004
IEEE
15 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
CODES
2004
IEEE
15 years 10 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ECOOPWEXCEPTION
2006
Springer
15 years 10 months ago
Exception Handling and Asynchronous Active Objects: Issues and Proposal
Asynchronous Active Objects (AAOs), primarily exemplied by actors [1], nowadays exist in many forms (various kinds of actors, agents and components) and are more and more used beca...
Christophe Dony, Christelle Urtado, Sylvain Vautti...
« Prev « First page 1906 / 2182 Last » Next »