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DAC
1999
ACM
16 years 7 months ago
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
Jason Cong, Honching Li, Chang Wu
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
16 years 7 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
16 years 29 days ago
CMOS Control Enabled Single-Type FET NASIC
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
Pritish Narayanan, Michael Leuchtenburg, Teng Wang...
ISCAS
2006
IEEE
70views Hardware» more  ISCAS 2006»
16 years 18 days ago
A portable all-digital pulsewidth control loop for SOC applications
—A cell-based all-digital PWCL is presented in this paper. To improve design effort as well as facilitate systemlevel integration, the new design can be developed in hardware des...
Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu
ARITH
2005
IEEE
16 years 6 days ago
Efficient Mapping of Addition Recurrence Algorithms in CMOS
Efficient adder design requires proper selection of a recurrence algorithm and its realization. Each of the algorithms: Weinberger’s, Ling’s and Doran’s were analyzed for it...
Bart R. Zeydel, Theo T. J. H. Kluter, Vojin G. Okl...