Sciweavers

6147 search results - page 104 / 1230
» Requirements, Architectures and Risks
Sort
View
KBSE
2003
IEEE
15 years 11 months ago
An Approach for Tracing and Understanding Asynchronous Architectures
Applications built in a strongly decoupled, eventbased interaction style have many commendable characteristics, including ease of dynamic configuration, accommodation of platform ...
Scott A. Hendrickson, Eric M. Dashofy, Richard N. ...
ICDE
2008
IEEE
119views Database» more  ICDE 2008»
16 years 7 months ago
Toward Simulation-Based Optimization in Data Stream Management Systems
Abstract-- Our demonstration introduces a novel system architecture which massively facilitates optimization in data stream management systems (DSMS). The basic idea is to decouple...
Bernhard Seeger, Christoph Heinz, Jürgen Kr&a...
DAC
2007
ACM
15 years 10 months ago
Design for Verification in System-level Models and RTL
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
Anmol Mathur, Venkat Krishnaswamy
ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
15 years 10 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
VLSID
2006
IEEE
136views VLSI» more  VLSID 2006»
16 years 6 months ago
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal
Serial links in network on chip provide advantages in terms of reduced wiring area, reduced switch complexity and power. However, serial links offer lower bandwidth in comparison ...
Simon Ogg, Bashir M. Al-Hashimi