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DAC
2004
ACM
15 years 12 months ago
A timing-driven module-based chip design flow
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
Fan Mo, Robert K. Brayton
INTELLCOMM
2004
Springer
15 years 11 months ago
On Using WS-Policy, Ontology, and Rule Reasoning to Discover Web Services
This paper proposes an approach to behaviour-based discovery of Web Services by which business rules that govern service behaviour are described as a policy. The policy is represen...
Natenapa Sriharee, Twittie Senivongse, Kunal Verma...
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
15 years 11 months ago
Noise Macromodel for Radio Frequency Integrated Circuits
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
DFT
2003
IEEE
98views VLSI» more  DFT 2003»
15 years 11 months ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao
ICDAR
2003
IEEE
15 years 11 months ago
Engineering Drawings Recognition Using a Case-based Approach
In this paper, we propose a framework for engineering drawings recognition using a case-based approach. The key idea of our scheme is that, interactively, the user provides an exa...
Yan Luo, Liu Wenyin