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ICCAD
2007
IEEE
87views Hardware» more  ICCAD 2007»
16 years 3 months ago
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
Philip Brisk, Ajay K. Verma, Paolo Ienne
159
Voted
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
16 years 3 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
CVPR
2010
IEEE
16 years 3 months ago
Surface Extraction from Binary Volumes with Higher-Order Smoothness
A number of 3D shape reconstruction algorithms, in particular 3D image segmentation methods, produce their results in the form of binary volumes, where a binary value indicates whe...
Victor Lempitsky
CVPR
2010
IEEE
16 years 2 months ago
A Square-Root Sampling Approach to Fast Histogram-Based Search
We present an efficient pixel-sampling technique for histogram-based search. Given a template image as a query, a typical histogram-based algorithm aims to find the location of ...
Huang-Wei Chang, Hwann-Tzong Chen
ETRA
2010
ACM
143views Biometrics» more  ETRA 2010»
16 years 1 months ago
Space-variant spatio-temporal filtering of video for gaze visualization and perceptual learning
We introduce an algorithm for space-variant filtering of video based on a spatio-temporal Laplacian pyramid and use this algorithm to render videos in order to visualize prerecor...
Michael Dorr, Halszka Jarodzka, Erhardt Barth