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» Reliability-Centric High-Level Synthesis
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FDL
2007
IEEE
16 years 6 days ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
IPPS
2007
IEEE
16 years 5 days ago
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs
Maik Boden, Thomas Fiebig, Torsten Meibner, Steffe...
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
15 years 11 months ago
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
Rafael Ruiz-Sautua, María C. Molina, Jos&ea...
163
Voted
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
15 years 11 months ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
133
Voted
ASAP
2000
IEEE
96views Hardware» more  ASAP 2000»
15 years 10 months ago
High-Level Synthesis of Nonprogrammable Hardware Accelerators
Robert Schreiber, Shail Aditya, B. Ramakrishna Rau...