Sciweavers

6568 search results - page 974 / 1314
» Reducing the Complexity of Reductions
Sort
View
GTTSE
2007
Springer
16 years 29 days ago
Model Transformations for the Compilation of Multi-processor Systems-on-Chip
With the increase of amount of transistors which can be contained on a chip and the constant expectation for more sophisticated applications, the design of Systems-on-Chip (SoC) is...
Éric Piel, Philippe Marquet, Jean-Luc Dekey...
LCTRTS
2007
Springer
16 years 28 days ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
CODES
2006
IEEE
16 years 26 days ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
IJCNN
2006
IEEE
16 years 25 days ago
Sparse Bayesian Models: Bankruptcy-Predictors of Choice?
Abstract— Making inferences and choosing appropriate responses based on incomplete, uncertainty and noisy data is challenging in financial settings particularly in bankruptcy de...
Bernardete Ribeiro, Armando Vieira, João Ca...
172
Voted
ISSTA
2006
ACM
16 years 23 days ago
Coverage and adequacy in software product line testing
Software product line modeling has received a great deal of attention for its potential in fostering reuse of software artifacts across development phases. Research on the testing...
Myra B. Cohen, Matthew B. Dwyer, Jiangfan Shi