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ISQED
2008
IEEE
150views Hardware» more  ISQED 2008»
16 years 1 months ago
Fundamental Data Retention Limits in SRAM Standby Experimental Results
SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is ofte...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
153
Voted
ICON
2007
IEEE
16 years 1 months ago
A New Pre-emption Policy For MPLS-TE Networks
— The pre-emption mechanism may be used in Multi Protocol Label Switching Traffic Engineering (MPLS-TE) networks in order to reduce the number of rejected tunnels during failure...
Imène Chaieb, Jean-Louis Le Roux, Bernard C...
GLVLSI
2006
IEEE
142views VLSI» more  GLVLSI 2006»
16 years 28 days ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
Kiran Puttaswamy, Gabriel H. Loh
ISLPED
2005
ACM
101views Hardware» more  ISLPED 2005»
16 years 13 days ago
Defocus-aware leakage estimation and control
Leakage power is one of the most critical issues for ultra-deep submicron technology. Subthreshold leakage depends exponentially on linewidth, and consequently variation in linewi...
Andrew B. Kahng, Swamy Muddu, Puneet Sharma
187
Voted
IEEEPACT
1999
IEEE
15 years 11 months ago
Predicated Static Single Assignment
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...