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» Reducing the Complexity of Reductions
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VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
16 years 7 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...
HPCA
2005
IEEE
16 years 7 months ago
Distributing the Frontend for Temperature Reduction
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
Antonio González, Grigorios Magklis, Jos&ea...
HPCA
2005
IEEE
16 years 7 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
16 years 3 months ago
Reduction of Crosstalk Pessimism using Tendency Graph Approach
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred ...
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 3 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes