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TIM
2010
294views Education» more  TIM 2010»
15 years 1 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
SCN
2010
Springer
122views Communications» more  SCN 2010»
15 years 5 months ago
Recursive Lattice Reduction
Abstract. Lattice reduction is known to be a very powerful tool in modern cryptanalysis. In the literature, there are many lattice reduction algorithms that have been proposed with...
Thomas Plantard, Willy Susilo
DAC
2003
ACM
16 years 7 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
DAC
2005
ACM
16 years 7 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
MICCAI
2006
Springer
16 years 7 months ago
Shape Filtering for False Positive Reduction at Computed Tomography Colonography
Abstract. In this paper, we treat the problem of reducing the false positives (FP) in the automatic detection of colorectal polyps at Computer Aided Detection in Computed Tomograph...
Abhilash A. Miranda, Tarik A. Chowdhury, Ovidiu Gh...