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» Reducing the Complexity of Reductions
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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 12 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
196
Voted
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 11 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
ICC
2000
IEEE
147views Communications» more  ICC 2000»
15 years 11 months ago
Average Power Reduction Techniques for Multiple-Subcarrier Intensity-Modulated Optical Signals
Abstract—We describe two classes of simple, effective techniques for reducing the average optical power requirement in intensity-modulated optical systems using multiple BPSK or ...
Roy You, Joseph M. Kahn
AWIC
2004
Springer
15 years 10 months ago
Attribute Reduction for Effective Intrusion Detection
Abstract. Computer intrusion detection is to do with identifying computer activities that may compromise the integrity, confidentiality or the availability of an IT system. Anomaly...
Fernando Godínez, Dieter Hutter, Raul Monro...
GECCO
2008
Springer
158views Optimization» more  GECCO 2008»
15 years 7 months ago
Objective reduction using a feature selection technique
This paper introduces two new algorithms to reduce the number of objectives in a multiobjective problem by identifying the most conflicting objectives. The proposed algorithms ar...
Antonio López Jaimes, Carlos A. Coello Coel...