6568 search results - page 191 / 1314 » Reducing the Complexity of Reductions |
178
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IPCCC
2006
IEEE
16 years 18 days ago
2006
IEEE
— This paper presents an investment strategy to reduce the risk associated with failures in Wavelength Division Multiplexing (WDM) optical networks. The investment strategy deter...
152
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ASPDAC
2006
ACM
16 years 17 days ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
148
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DATE
2005
IEEE
16 years 6 days ago
2005
IEEE
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
175
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DATE
2005
IEEE
16 years 6 days ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
211
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WOLLIC
2010
Springer
15 years 11 months ago
2010
Springer
Abstract. The intruder deduction problem for an electronic purse protocol with blind signatures is considered. The algebraic properties of the protocol are modeled by an equational...