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» Reducing the Complexity of Reductions
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ICDM
2002
IEEE
158views Data Mining» more  ICDM 2002»
15 years 11 months ago
Adaptive dimension reduction for clustering high dimensional data
It is well-known that for high dimensional data clustering, standard algorithms such as EM and the K-means are often trapped in local minimum. Many initialization methods were pro...
Chris H. Q. Ding, Xiaofeng He, Hongyuan Zha, Horst...
FPL
2009
Springer
152views Hardware» more  FPL 2009»
15 years 11 months ago
Clock gating architectures for FPGA power reduction
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
Safeen Huda, Muntasir Mallick, Jason H. Anderson
IDEAS
2000
IEEE
117views Database» more  IDEAS 2000»
15 years 11 months ago
Path Query Reduction and Diffusion for Distributed Semi-Structured Data Retrieval
I n this paper, we address the problem of query processing o n distributed semi-structured data. The distributed semistructured data can be modeled as a rooted and edge-labeled gr...
Jaehyung Lee, Yon Dohn Chung, Myoung-Ho Kim
SIGMETRICS
1999
ACM
130views Hardware» more  SIGMETRICS 1999»
15 years 11 months ago
Address Trace Compression Through Loop Detection and Reduction
ded Abstract This paper introduces a new technique for compressing memory address traces. The technique relies on the simple observation that most programs spend their time execut...
E. N. Elnozahy
ISCAS
1999
IEEE
77views Hardware» more  ISCAS 1999»
15 years 11 months ago
Power reduction through iterative gate sizing and voltage scaling
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, W...