6568 search results - page 147 / 1314 » Reducing the Complexity of Reductions |
150
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective sp...
147
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
This paper presents a class of algorithms suitable for model reduction of distributed systems. Distributed systems are not suitable for treatment by standard model-reduction algor...
192
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
164
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
141
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...