6568 search results - page 132 / 1314 » Reducing the Complexity of Reductions |
196
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ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
15 years 4 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
148
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ICIP
2009
IEEE
15 years 4 months ago
2009
IEEE
This paper presents a fast algorithm for H.264 fractional motion estimation (ME). In H.264 ME is the most time consuming component. The ME process consists of two stages: integer ...
200
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CEC
2011
IEEE
14 years 6 months ago
2011
IEEE
—Despite the range of applications and successes of evolutionary algorithms, expensive fitness computations often form a critical performance bottleneck. A preferred method of r...
165
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ICCD
2008
IEEE
16 years 3 months ago
2008
IEEE
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
189
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ICCD
2003
IEEE
16 years 3 months ago
2003
IEEE
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...