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ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
16 years 26 days ago
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihar...
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
16 years 16 days ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
ICIP
2005
IEEE
16 years 2 days ago
Interactive 3D filter design for ultrasound artifact reduction
A method for detecting and reducing reverberation artifacts in ultrasound image sequences is described. A reverberation artifact localization map is produced using local Rf-bandwi...
Nina Eriksson Bylund, Mats T. Andersson, Hans Knut...
APCCAS
2002
IEEE
157views Hardware» more  APCCAS 2002»
15 years 11 months ago
Multiplier energy reduction through bypassing of partial products
Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital mul...
Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue
MICRO
2000
IEEE
122views Hardware» more  MICRO 2000»
15 years 11 months ago
Dynamic zero compression for cache energy reduction
Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is i...
Luis Villa, Michael Zhang, Krste Asanovic