6568 search results - page 124 / 1314 » Reducing the Complexity of Reductions |
140
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing...
136
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ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we propose efficient techniques and architectures for realizing spatial-downscaling transcoders in the DCT domain. We also present methods for re-sampling motion ve...
172
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VTS
2002
IEEE
15 years 11 months ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
161
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WSC
2007
15 years 8 months ago
2007
The Logistics Composite Model (LCOM) is a stochastic, discrete-event simulation that relies on probabilities and random number generators to model scenarios in a maintenance unit ...
175
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...