We extend an existing probabilistic congestion model to consider shielding for crosstalk reduction. We then develop a multilevel router to study the impact of various congestion m...
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, ...
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate le...