6568 search results - page 114 / 1314 » Reducing the Complexity of Reductions |
156
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ISQED
2006
IEEE
16 years 14 days ago
2006
IEEE
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
149
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ISLPED
2005
ACM
16 years 15 hour ago
2005
ACM
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
163
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VLSID
2009
IEEE
16 years 7 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
151
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FPGA
2009
ACM
16 years 1 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
186
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ASPDAC
2010
ACM
15 years 4 months ago
2010
ACM
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...