6568 search results - page 1105 / 1314 » Reducing the Complexity of Reductions |
191
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CASES
2006
ACM
15 years 10 months ago
2006
ACM
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
175
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
171
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DATE
2004
IEEE
2004
IEEE
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
15 years 10 months ago
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
153
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
175
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...