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ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
16 years 25 days ago
A Real Case of Significant Scan Test Cost Reduction
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Selina Sha, Bruce Swanson
IPPS
2003
IEEE
15 years 11 months ago
Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors
While prefetch has proven itself useful for reducing cache misses in multiprocessors, traffic is often increased due to extra unused prefetch data. Prefetching in multiprocessors...
Dan Wallin, Erik Hagersten
SIMPRA
1998
99views more  SIMPRA 1998»
15 years 6 months ago
Rollback overhead reduction methods for time warp distributed simulation
Parallel discrete event simulation is a useful technique to improve performance of sequential discrete event simulation. We consider the Time Warp algorithm for asynchronous distr...
Simonetta Balsamo, C. Manconi
ICSE
2008
IEEE-ACM
16 years 7 months ago
An empirical study of the effects of test-suite reduction on fault localization
Fault-localization techniques that utilize information about all test cases in a test suite have been presented. These techniques use various approaches to identify the likely fau...
Yanbing Yu, James A. Jones, Mary Jean Harrold
ICIP
2006
IEEE
16 years 8 months ago
Bit Rate Reduction of Vector Representation of Binary Images
Vector representation of binary images has an advantage of keeping high image quality for arbitrary scaling as well as editing capability of an object. However, the vector represe...
Yuki Yamamoto, Kei Kawamura, Hiroshi Watanabe