3702 search results - page 308 / 741 » Reducing Misclassification Costs |
211
click to vote
ICDCS
1997
IEEE
15 years 11 months ago
1997
IEEE
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
156
click to vote
MICRO
1997
IEEE
15 years 11 months ago
1997
IEEE
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
154
click to vote
ISCA
1996
IEEE
15 years 10 months ago
1996
IEEE
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
191
click to vote
DAC
1996
ACM
15 years 10 months ago
1996
ACM
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
144
click to vote
EURODAC
1994
IEEE
15 years 10 months ago
1994
IEEE
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...