26 search results - page 3 / 6 » Reconfigurable synchronized dataflow processor |
176
Voted
DAC
2007
ACM
16 years 6 months ago
2007
ACM
Abstract. Embedded multimedia systems often run multiple time-constrained applications simultaneously. These systems use multiprocessor systems-on-chip of which it must be guarante...
149
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ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
141
Voted
DATE
2002
IEEE
15 years 10 months ago
2002
IEEE
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
175
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TCAD
2010
15 years 15 days ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
167
Voted
PROCEDIA
2010
15 years 16 days ago
2010
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...