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DATE
2008
IEEE
115views Hardware» more  DATE 2008»
16 years 1 months ago
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
FCCM
2005
IEEE
93views VLSI» more  FCCM 2005»
16 years 5 days ago
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...
Zion Kwok, Steven J. E. Wilton
CODES
2002
IEEE
15 years 11 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
EUROPAR
2006
Springer
15 years 10 months ago
Supporting Reconfigurable Parallel Multimedia Applications
Abstract. Programming multimedia applications for System-on-Chip (SoC) architectures is difficult because streaming communication, user event handling, reconfiguration, and paralle...
Maik Nijhuis, Herbert Bos, Henri E. Bal
HPCN
2000
Springer
15 years 10 months ago
Dynamic Reconfiguration in Coordination Languages
A rather recent approach in programming parallel and distributed systems is that of coordination models and languages. Coordination programming enjoys a number of advantages such a...
George A. Papadopoulos, Farhad Arbab