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ICPADS
2006
IEEE
16 years 19 days ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
IPPS
2006
IEEE
16 years 19 days ago
Empowering a helper cluster through data-width aware instruction selection policies
Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- a...
Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio G...
IPPS
2006
IEEE
16 years 19 days ago
Improving cache locality for thread-level speculation
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
Stanley L. C. Fung, J. Gregory Steffan
PLDI
2004
ACM
16 years 1 days ago
Cost effective dynamic program slicing
Although dynamic program slicing was first introduced to aid in user level debugging, applications aimed at improving software quality, reliability, security, and performance hav...
Xiangyu Zhang, Rajiv Gupta
CHI
2010
ACM
15 years 12 months ago
Estimating residual error rate in recognized handwritten documents using artificial error injection
Both handwriting recognition systems and their users are error prone. Handwriting recognizers make recognition errors, and users may miss those errors when verifying output. As a ...
Edward Lank, Ryan Stedman, Michael Terry
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