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ASPDAC
2007
ACM
152views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Graph Reduction Approach to Symbolic Circuit Analysis
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
Guoyong Shi, Weiwei Chen, C.-J. Richard Shi
ACL
2007
15 years 8 months ago
Regression for Sentence-Level MT Evaluation with Pseudo References
Many automatic evaluation metrics for machine translation (MT) rely on making comparisons to human translations, a resource that may not always be available. We present a method f...
Joshua Albrecht, Rebecca Hwa
SBACPAD
2004
IEEE
124views Hardware» more  SBACPAD 2004»
15 years 8 months ago
Improving Parallel Execution Time of Sorting on Heterogeneous Clusters
The aim of the paper is to introduce techniques in order to optimize the parallel execution time of sorting on heterogeneous platforms (processors speeds are related by a constant...
Christophe Cérin, Michel Koskas, Hazem Fkai...
NIPS
2000
15 years 8 months ago
The Use of Classifiers in Sequential Inference
We study the problem of combining the outcomes of several different classifiers in a way that provides a coherent inference that satisfies some constraints. In particular, we deve...
Vasin Punyakanok, Dan Roth
JSSPP
2007
Springer
16 years 28 days ago
New Challenges of Parallel Job Scheduling
Abstract. The workshop on job scheduling strategies for parallel processing (JSSPP) studies the myriad aspects of managing resources on parallel and distributed computers. These st...
Eitan Frachtenberg, Uwe Schwiegelshohn