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DATE
2009
IEEE
90views Hardware» more  DATE 2009»
16 years 1 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
GLOBECOM
2007
IEEE
16 years 1 months ago
A New Design of Bloom Filter for Packet Inspection Speedup
— Bloom filter is a space-efficient randomized data structure for group membership query. It is widely used in networking applications which involve the packet header/content i...
Yang Chen, Abhishek Kumar, Jun Xu
ISQED
2007
IEEE
150views Hardware» more  ISQED 2007»
16 years 1 months ago
A Design Methodology for Matching Improvement in Bandgap References
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significa...
Juan Pablo Martinez Brito, Hamilton Klimach, Sergi...
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
16 years 11 days ago
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...
CHI
2009
ACM
15 years 11 months ago
Getting sidetracked: display design and occasioning photo-talk with the photohelix
In this paper we discuss some of our recent research work designing tabletop interfaces for co-located photo sharing. We draw particular attention to a specific feature of an inte...
Otmar Hilliges, David Shelby Kirk