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IPPS
2007
IEEE
16 years 1 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ICN
2007
Springer
16 years 27 days ago
Design Issues of Peer-to-Peer Systems for Wireless Ad Hoc Networks
– Peer-to-peer is a popular distributed system. Mobile ad hoc networks and peer-to-peer file sharing systems both lack fixed infrastructure support and hold no a-priori knowledge...
Dewan Tanvir Ahmed, Shervin Shirmohammadi
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
16 years 24 days ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
16 years 10 days ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
168
Voted
RTAS
2005
IEEE
16 years 9 days ago
Robust Control/Scheduling Co-Design: Application to Robot Control
Control systems running on a computer are subject to timing disturbances coming from implementation constraints. Fortunately closed-loop systems behave robustly w.r.t. modelling e...
Daniel Simon, David Robert, Olivier Sename