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ICRA
2009
IEEE
176views Robotics» more  ICRA 2009»
16 years 1 months ago
Path planning in 1000+ dimensions using a task-space Voronoi bias
— The reduction of the kinematics and/or dynamics of a high-DOF robotic manipulator to a low-dimension “task space” has proven to be an invaluable tool for designing feedback...
Alexander C. Shkolnik, Russ Tedrake
ASIACRYPT
2009
Springer
16 years 1 months ago
Attacking Power Generators Using Unravelled Linearization: When Do We Output Too Much?
We look at iterated power generators si = se i−1 mod N for a random seed s0 ∈ ZN that in each iteration output a certain amount of bits. We show that heuristically an output of...
Mathias Herrmann, Alexander May
VTS
2003
IEEE
127views Hardware» more  VTS 2003»
16 years 10 days ago
Bist Reseeding with very few Seeds
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of determinist...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
ASPDAC
1999
ACM
112views Hardware» more  ASPDAC 1999»
15 years 11 months ago
Relaxed Simulated Tempering for VLSI Floorplan Designs
In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new...
Jason Cong, Tianming Kong, Dongmin Xu, Faming Lian...
DAC
1995
ACM
15 years 10 months ago
Power Estimation in Sequential Circuits
Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences t...
Farid N. Najm, Shashank Goel, Ibrahim N. Hajj