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FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
15 years 10 months ago
Mixing buffers and pass transistors in FPGA routing architectures
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
Mike Sheng, Jonathan Rose
FOCS
2000
IEEE
15 years 10 months ago
Nearly Optimal Expected-Case Planar Point Location
We consider the planar point location problem from the perspective of expected search time. We are given a planar polygonal subdivision S and for each polygon of the subdivision t...
Sunil Arya, Theocharis Malamatos, David M. Mount
SMA
1999
ACM
106views Solid Modeling» more  SMA 1999»
15 years 10 months ago
Resolving non-uniqueness in design feature histories
Nearly all major commercial computer-aided design systems have adopted a feature-based design approach to solid modeling. Models are created via a sequence of operations which app...
Vincent A. Cicirello, William C. Regli
RTCSA
1999
IEEE
15 years 10 months ago
A Symbolic Model Checker for Testing ASTRAL Real-Time Specifications
ASTRAL is a high-level formal specification language for real-time (infinite state) systems. It is provided with structuring mechanisms that allow one to build modularized specifi...
Zhe Dang, Richard A. Kemmerer
SIGCOMM
1998
ACM
15 years 10 months ago
The MASC/BGMP Architecture for Inter-Domain Multicast Routing
Multicast routing enables e cient data distribution to multiple recipients. However, existing work has concentrated on extending single-domain techniques to wide-area networks, ra...
Satish Kumar, Pavlin Radoslavov, David Thaler, Cen...